1. Field of the Invention
The invention relates in general to a method and a circuit for decoding a received command, and more particularly to a method and a circuit for decoding a received command for improving the efficiency of a memory device.
2. Description of the Related Art
FIG. 1 is a timing diagram showing the timing diagram of a number of signals in a conventional command decoder when the command decoder decodes a received command. In general, command decoder can be used in a memory device for decoding commands from a host device. The command decoder receives a number of input signals SIO[3:0] in parallel (including signals SIO[3], SIO[2], SIO[1], and SIO[0] which are received in parallel by four pins) through which the encoded data of a command is delivered, and decodes the encoded data to generate a starting signal MODE to make the memory device to perform a corresponding operation. In a conventional command decoder, however, the starting signal MODE lags behind the input signals SIO[3:0] for the sum of at least three time delays t1, t2, and t3 as shown in FIG. 1, which is detailed as follows.
The command decoder is usually operated with reference to an external clock signal SCK, which allows internal circuits of the memory device to be operated synchronously. The encoded data of the command are delivered through the input signals SIO[3:0] with respect to different pulse duration of the external clock signal SCK. For example, as shown FIG. 1, the command includes 8-bit encoded data, in which upper 4-bit encoded data CMD[3:0] are delivered through the input signals SIO[3:0] with respect to a first pulse duration D1 of the external clock signal SCK, and lower 4-bit encoded data CMD[7:4] are delivered through the input signals SIO[3:0] with respect to a second pulse duration D2 of the external clock signal SCK. The input signals SIO[3:0] usually lead ahead the external clock signal SCK under the requirement of setup time and hold time. In this regard, the external clock signal SCK will lag behind the input signal SIO for a time delay t1, as shown in FIG. 1.
Moreover, the external clock signal SCK can be converted by circuit elements into an internal clock signal CLK which is used as a reference clock for sampling and decoding the encoded data of the command obtained from the input signals SIO[3:0]. As such, the internal clock signal CLK for decoding will lag behind the external clock signal SCK for a time delay t2 due to signal transmission delay in the circuit elements. Furthermore, in the course of decoding, the encoded data is sampled at the rising edge of the internal clock signal CLK. Next, logical operation is performed on the encoded data so as to decode the command. As a result, a time delay t3 exists between the internal clock signal CLK and the starting signal MODE.
Such time delays t1 to t3 affect the efficiency of the memory device. The reason is that a time point T at which the starting signal MODE is generated is so late and only time period P is left for the memory device to perform the corresponding operation of the starting signal MODE. In addition, under this situation, for maintaining enough length of the time period P, the period of the clock signal SCK can not be shortened, which causes that the frequency of the external clock signal SCK can not be increased and the efficiency of the memory device can not be increased. Therefore, it is a subject of the industrial endeavors to improve the efficiency of the memory device.